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| www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 * * * * * * * * * * * * * * Double data rate architecture: two data transfers per clock cycle * Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver * DQS is edge-aligned with data for reads and is centeraligned with data for writes * Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8s Maximum Average Periodic Refresh Interval SSTL_2 compatible I/O interface VDDQ = 2.6V 0.1V VDD = 2.6V 0.1V Lead-free and Halogen-free product available Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecThe 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation. The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time. interface designed to transfer two data words per clock cycle .com refresh mode is provided along with a power-saving DataShee An auto at the I/O pins. A single read or write access for the 256Mb Power Down mode. All inputs are compatible with the JEDEC DDR SDRAM effectively consists of a single 2n-bit wide, one Standard for SSTL_2. All outputs are SSTL_2, Class II comclock cycle data transfer at the internal DRAM core and two patible. corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS of operation. is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge func- REV 1.3 .com 06/2003 1 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Pin Configuration - 400mil TSOP II (x4 / x8 / x16) VD D NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VD D NU NC WE CAS VDD DQ0 VDDQ NC DQ1 V SSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VD D VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NU LDM* WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 NC V SSQ UDQS NC V REF V SS UDM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 V SS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 V SS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 V SS t4U.com RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD .com 23 44 24 25 26 27 28 29 30 31 32 33 43 42 41 40 39 38 37 36 35 34 DataShee 66-pin Plastic TSOP-II 400mil 16Mb x 16 32Mb x 8 64Mb x 4 Column Address Table Organization 64Mb x 4 32Mb x 8 16Mb x 16 Column Address A0-A9, A11 A0-A9 A0-A8 *DM is internally loaded to match DQ and DQS identically. REV 1.3 .com 06/2003 2 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package 64 X 4 1 VSSQ NC NC NC NC VREF 2 NC VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 3 VSS DQ3 NC DQ2 DQS DQM CLK CKE A9 A7 A B C D E F G H J K 7 VDD DQ0 NC DQ1 QFC NC WE RAS BA1 A0 8 NC VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3 9 VDDQ NC NC NC NC NC t4U.com A6 A4 .com A5 L A2 VSS M VDD DataShee 32 X 8 1 VSSQ NC NC NC NC VREF 2 DQ7 VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 A6 A4 3 VSS DQ6 DQ5 DQ4 DQS DQM CLK CKE A9 A7 A5 VSS A B C D E F G H J K L M 7 VDD DQ1 DQ2 DQ3 QFC NC WE RAS BA1 A0 A2 VDD 8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3 9 VDDQ NC NC NC NC NC REV 1.3 .com 06/2003 3 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package 16 X 16 1 VSSQ DQ14 DQ12 DQ10 DQ8 VREF 2 DQ15 VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 A6 3 VSS DQ13 DQ11 DQ9 DQS DQM CLK CKE A9 A7 A5 A B C D E F G H J K L 7 VDD DQ2 DQ4 DQ6 LDQS LDW WE RAS BA1 A0 A2 8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3 9 VDDQ DQ1 DQ3 DQ5 DQ7 NC t4U.com A4 .com VSS M VDD DataShee REV 1.3 .com 06/2003 4 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Input/Output Functional Description Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices. Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0, to allow upper or lower deck selection on stacked devices. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and .com Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0DQ7; UDQS corresponds to the data on DQ8-DQ15 No Connect: No internal electrical connection is present. Electrical connection is present. Should not be connected at second level of assembly. Supply Supply Supply Supply Supply DQ Power Supply: 2.6V 0.1V. DQ Ground Power Supply: 2.6V 0.1V. Ground SSTL_2 reference voltage: (V DDQ / 2) 1%. CKE, CKE0, CKE1 Input CS, CS0, CS1 Input RAS, CAS , WE Input DM Input BA0, BA1 Input t4U.com A0 - A12 Input DataShee DQ DQS, LDQS, UDQS NC NU V DDQ V SSQ V DD V SS V REF Input/Output Input/Output REV 1.3 .com 06/2003 5 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Ordering Information Speed Org. Part Number NT5DS64M4BT-5T 64M x 4 NT5DS64M4BF-5T NT5DS32M8BT-5T 32M x 8 NT5DS32M8BF-5T NT5DS16M16BT-5T 16M x 16 NT5DS16M16BF-5T NT5DS64M4BS-5T1 64M x 4 NT5DS64M4BG-5T 1 NT5DS32M8BS-5T1 32M x 8 NT5DS32M8BG-5T 1 NT5DS16M16BS-5T 1 16M x 16 NT5DS16M16BG-5T 1 Package Clock (MHz) 66 pin TSOP-II 60ball BGA 0.8mmx1.0mm Pitch 66 pin TSOP-II 60ball BGA 0.8mmx1.0mm Pitch 66 pin TSOP-II 60ball BGA 0.8mmx1.0mm Pitch 66 pin TSOP-II 60ball BGA 0.8mmx1.0mm Pitch 66 pin TSOP-II 60ball BGA 0.8mmx1.0mm Pitch 66 pin TSOP-II 60ball BGA 0.8mmx1.0mm Pitch 200 200 200 200 200 200 200 200 200 200 200 200 CL-tRCD-tRP 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 3-3-3/3-4-4 Clock (MHz) 166 166 166 166 166 166 166 166 166 166 166 166 CL-tRCD -tRP 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 DDR400B DDR400B DDR400B DDR400B DDR400B DDR400B DDR400B DDR400B DDR400B DDR400B DDR400B DDR400B Comments t4U.com .com DataShee Note: 1. Lead-free and Halogen-free product 2. At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information only REV 1.3 .com 06/2003 6 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Block Diagram (64Mb x 4) Control Logic CKE CK CK CS WE CAS RAS Command Decode Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder Bank2 Bank3 CK, CK DLL Mode Registers 13 8192 Read Latch Refresh Counter 13 4 4 MUX 4 DQS Generator 1 Sense Amplifiers Bank Control Logic 8192 8 Drivers 15 13 Bank0 Memory Array (8192 x 1024 x 8) Data Address Register A0-A12, BA0, BA1 2 15 I/O Gating DM Mask Logic 1024 (x8) Column Decoder 10 COL0 8 8 Write FIFO & Drivers clk clk out in CK, CK Input Register Mask 1 1 2 8 Data COL0 1 4 4 1 4 4 1 4 DQS DQ0-DQ3, DM DQS 2 11 Column-Address Counter/Latch 1 COL0 t4U.com 1 .com Receivers DataShee Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. REV 1.3 .com 06/2003 7 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Block Diagram (32Mb x 8) Control Logic CKE CK CK CS WE CAS RAS Command Decode Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder Bank2 Bank3 CK, CK DLL Mode Registers 13 8192 Read Latch Refresh Counter 13 8 8 MUX 8 DQS Generator 1 Sense Amplifiers Bank Control Logic 8192 16 Drivers 15 13 Bank0 Memory Array (8192 x 512 x 16) Data Address Register A0-A12, BA0, BA1 2 15 I/O Gating DM Mask Logic 512 (x16) COL0 16 16 Write FIFO & Drivers Input Register 1 Mask 1 2 16 1 8 1 8 8 DQS 1 8 Receivers DQ0-DQ7, DM DQS 2 Column Decoder 9 10 Column-Address Counter/Latch 1 COL0 8 clk clk out in Data CK, CK COL0 t4U.com .com 1 DataShee Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. REV 1.3 .com 06/2003 8 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Block Diagram (16Mb x 16) Control Logic CKE CK CK CS WE CAS RAS Command Decode Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder Bank2 Bank3 CK, CK DLL Mode Registers 13 8192 Read Latch Refresh Counter 13 16 16 MUX 16 DQS Generator 1 Sense Amplifiers Bank Control Logic 8192 32 Drivers 15 13 Bank0 Memory Array (8192 x 256 x 32) Data Address Register A0-A12, BA0, BA1 2 15 I/O Gating DM Mask Logic 256 (x32) COL0 32 32 Write FIFO & Drivers Input Register 1 Mask 1 2 32 1 16 1 16 16 DQS 1 16 Receivers DQ0-DQ15, LDM, UDM LDQS,UDQS 2 Column Decoder 8 9 Column-Address Counter/Latch 1 COL0 16 clk clk out in Data CK, CK COL0 t4U.com .com 1 DataShee Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. REV 1.3 .com 06/2003 9 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization Only one of the following two conditions must be met. * No power sequencing is specified during power up or power down given the following criteria: VDD and VDDQ are driven from a single power converter output VTT meets the specification A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and .com t4U.com VREF tracks VDDQ /2 or * The following relationships must be followed: VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL command should be applied, placing the device in the "all banks idle" state Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. DDR SDRAM's may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or extended mode register can be modified at any valid time during device operation without affecting the state of the internal address refresh counters used for device refresh. DataShee REV 1.3 .com 06/2003 10 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Register Definition Mode Register The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2 -Ai when the burst length is set to four and by A3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length .com t4U.com applies to both Read and Write bursts. DataShee REV 1.3 .com 06/2003 11 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Mode Register Operation BA1 0* BA0 0* A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Address Bus Mode Register Operating Mode CAS Latency Burst Length A12 - A9 0 0 0 A8 0 1 0 A7 0 0 1 A6 - A0 Valid Valid VS** Operating Mode Normal operation Do not reset DLL Normal operation in DLL Reset Vendor-Specific Test Mode Reserved A3 0 1 Burst Type Sequential Interleave - - - CAS Latency A6 0 0 0 0 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved 2.5 Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved t4U.com 1 1 1 1 .com 1.5 (Option) DataShee VS ** Vendor Specific * BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register). REV 1.3 .com 06/2003 12 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Burst Definition Starting Column Address Burst Length A2 2 0 0 4 1 1 0 0 0 0 8 1 1 1 1 0 0 1 1 0 0 1 1 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Order of Accesses Within a Burst t4U.com Notes: 1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 13. Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2.5 or 3 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. .com DataShee REV 1.3 .com 06/2003 13 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. CAS Latencies CAS Latency = 3, BL = 4 CK CK Command Read NOP CL=3 DQS DQ NOP NOP NOP NOP t4U.com CK CK Command Read .com CAS Latency = 2.5, BL = 4 DataShee NOP CL=2.5 NOP NOP NOP NOP DQS DQ Shown with nominal t AC, tDQSCK , and tDQSQ . Don't Care REV 1.3 .com 06/2003 14 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM's (Exit Self Refresh to Read Command). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (tMRD ) or 10 clocks after the DLL is enabled via self refresh exit command (t XSNR, Exit Self Refresh to Non-Read Command). Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. QFC Enable/Disable t4U.com The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by .com hee means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature DataS for NANYA and is not included on all DDR SDRAM devices. REV 1.3 .com 06/2003 15 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Extended Mode Register Definition BA1 0* BA0 1* A 12 A 11 A 10 A9 A8 A7 A6 A5 A4 A3 A2 QFC A1 DS A0 DLL Address Bus Extended Mode Register Operating Mode Drive Strength A12 - A3 0 A2 - A0 Valid Operating Mode Normal Operation All other states Reserved 0 1 Normal Reserved A1 Drive Strength - - A2 0 1 QFC Disable Enable (Optional) A0 0 DLL Enable Disable * BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register) 1 t4U.com .com DataShee REV 1.3 .com 06/2003 16 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 4 DataSheet U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Commands Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each commands follows. Truth Table 1a: Commands Name (Function) Deselect (Nop) No Operation (Nop) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set CS H L L L L L L L L RAS X H L H H H L L L CAS X H H L L H H L L WE X H H H L L L H L Address X X Bank/Row Bank/Col Bank/Col X Code X Op-Code MNE NOP NOP ACT Read Write BST PRE AR / SR MRS Notes 1, 9 1, 9 1, 3 1, 4 1, 4 1, 8 1, 5 1, 6, 7 1, 2 t4U.com 1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. B A0-BA1 provide bank address and A0-A 12 provide row address. 4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre.com charge feature (non-persistent), A10 low disables the Auto Precharge feature. 5. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care." 6. This command is auto refresh if CKE is high; Self Refresh if CKE is low. 7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. Deselect and NOP are functionally interchangeable. DataShee Truth Table 1b: DM Operation Name (Function) Write Enable Write Inhibit 1. Used to mask write data; provided coincident with the corresponding data. DM L H DQs Valid X Notes 1 1 REV 1.3 .com 06/2003 17 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Deselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until t MRD is met. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. Read The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains .com t4U.com open for subsequent accesses. DataShee Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location. Precharge The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP ) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. REV 1.3 .com 06/2003 18 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is non-persistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is determined as if an explicit Precharge command was issued at the earliest possible time without violating t RAS(min). The user must not issue another command to the same bank until the precharge (t RP) is completed. The NTC DDR SDRAM devices supports the optional t RAS lockout feature. This feature allows a Read command with Auto Precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the t RAS(min) specification. The t RAS lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst length of data has been successfully prefetched from the memory array; and two, tRAS (min) has been satisfied. As a means to specify whether a DDR SDRAM device supports the t RAS lockout feature, a new parameter has been defined, tRAP (RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Precharge). For devices that support the tRAS lockout feature, tRAP = t RCD (min). This allows any Read Command (with or without Auto Precharge) to be issued to an open bank once tRCD (min) is satisfied. tRAP Definition CL=3, t CK =10ns CK CK Command NP O ACT NP O RD A NOP NOP NP O NP O ACT NP O NP O t4U.com DQ (BL=2) .com DQ0 DQ1 DataShee tRPmin NP O ACT NP O NP O tRASmin Command DQ (BL=4) NP O ACT NP O RD A NOP NOP * DQ1 NP O DQ0 DQ2 DQ3 Command DQ (BL=8) NP O ACT NP O RD A NOP NOP * DQ1 tRPmin NP O NOP ACT NP O NP O DQ0 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 tRCDmin tRAPmin The above timing diagrams show the effects of t RAP for devices that support t RAS lockout. In these cases, the Read with Auto Precharge command (RDA) is issued with tRCD (min) and dataout is available with the shortest latency from the Bank Activate command (ACT). The internal precharge operation, however, does not begin until after tRAS (min) is satisfied. * * tRPmin Indicates Auto Precharge begins here Burst Terminate The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write burst cycles are not to be terminated with the Burst Terminate command. REV 1.3 .com 06/2003 19 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Auto Refresh Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8s (maximum). Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are "Don't Care" during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. t4U.com .com DataShee REV 1.3 .com 06/2003 20 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Operations Bank/Row Activation Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened" (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the t RCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC . A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD . Activating a Specific Row in a Specific Bank CK CK CKE CS RAS CAS HIGH t4U.com WE A0-A12 BA0, BA1 .com RA = row address. BA = bank address. Don't Care DataShee RA BA REV 1.3 .com 06/2003 21 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM tRCD and t RRD Definition CK CK Command A0-A12 BA0, BA1 ACT NOP ACT NOP NOP RD/WR NOP NOP ROW BA x ROW BA y COL BA y tRRD tRCD Don't Care Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the .com t4U.com burst, provided t RAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled. During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). The following timing figure entitled "Read Burst: CAS Latencies (Burst Length=4)" illustrates the general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure entitled "Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)". A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data is shown in timing figure entitled "Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)". Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 27. DataShee REV 1.3 .com 06/2003 22 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Read Command CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care HIGH CA EN AP t4U.com .com DataShee REV 1.3 .com 06/2003 23 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 4 DataSheet U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Read Burst: CAS Latencies (Burst Length = 4) CAS Latency = 3 CK CK Command Address Read BA a,COL n NOP NOP NOP NOP NOP CL=3 DQS DQ tQCS QFC (Optional) DOa-n tQCH CAS Latency = 2.5 CK CK t4U.com Command Address Read BA a,COL n NOP .com NOP NOP NOP NOP DataShee CL=2.5 DQS DQ DOa-n QFC (Optional) tQ C S tQCH Don't Care DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC , tDQSCK , and t DQSQ . QFC is an open drain driver. The output high level is achieved through an external pull up resistor connected to V DDQ . REV 1.3 .com 06/2003 24 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8) CAS Latency = 3 CK CK Command Address Read NOP Read NOP NOP NOP BAa, COL n BAa, COL b CL=3 DQS DQ DOa-n DOa-b CAS Latency = 2.5 CK CK Command Read NOP Read NOP NOP NOP t4U.com Address BAa, COL n .com BAa,COL b DataShee CL=2.5 DQS DQ DOa- n DOa- b DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length = 4, the bursts are concatenated. When burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following DO a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b. Shown with nominal t AC , tDQSCK, and t DQSQ. Don't Care REV 1.3 .com 06/2003 25 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 4 DataSheet U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4) CAS Latency = 3 CK CK Command Address Read BAa, COL n NOP NOP Read BAa, COL b NOP NOP NOP CL=3 DQS DQ DO a- n DOa- b CAS Latency = 2.5 CK CK t4U.com Command Address Read NOP NOP .com BAa, COL b Read NOP NOP NOP DataShee BAa, COL n CL=2.5 DQS DQ DO a- n DOa- b DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a- b). Shown with nominal tAC , tDQSCK, and t DQSQ. Don't Care REV 1.3 .com 06/2003 26 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) CAS Latency = 3 CK CK Command Address Read BAa, COL n Read BAa, COL x Read BAa, COL b Read BAa, COL g NOP NOP CL=3 DQS DQ DOa-n DOa-n' DOa-x DOa-x' DOa- b DOa-b' CAS Latency = 2.5 CK CK Command Address Read Read Read Read NOP NOP t4U.com .com BAa, COL b DataShee BAa, COL g BAa, COL n BAa, COL x CL=2.5 DQS DQ DOa-n DOa- n' DOa-x DOa-x' DOa-b DOa-b' DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted). Reads are to active rows in any banks. Shown with nominal t AC , tDQSCK, and t DQSQ . Don't Care REV 1.3 .com 06/2003 27 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a Read Burst: CAS Latencies (Burst Length = 8) on page 29. The Burst Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data element pairs. Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst Length = 4 or 8) on page 30. The example is shown for t DQSS (min). The tDQSS (max) case, not shown here, has a longer bus idle time. t DQSS (min) and t DQSS(max) are defined in the section on Writes. A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Precharge: CAS Latencies (Burst Length = 4 or 8) on page 31 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be issued until t RP is met. Note that part of the row precharge time is hidden during the access of the last data elements. In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts. t4U.com .com DataShee REV 1.3 .com 06/2003 28 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Terminating a Read Burst: CAS Latencies (Burst Length = 8) CAS Latency = 3 CK CK Command Address Read BAa, COL n NOP BST NOP NOP NOP CL=3 DQS DQ DOa-n No further output data after this point. DQS tristated. CAS Latency = 2.5 CK CK t4U.com Command Address Read NOP BST .com NOP NOP NOP DataShee BAa, COL n CL=2.5 DQS DQ DOa-n No further output data after this point. DQS tristated. DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC , tDQSCK, and t DQSQ. Don't Care REV 1.3 .com 06/2003 29 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 4 DataSheet U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Read to Write: CAS Latencies (Burst Length = 4 or 8) CAS Latency = 3 CK CK Command Address Read BST NOP NOP NOP Write BAa, COL b BAa, COL n CL=3 DQS DQ DM DOa-n t DQSS (min) DIa-b CAS Latency = 2.5 CK t4U.com CK Command Address Read BAa, COL n .com BST NOP NOP Write BAa, COL b DataShee NOP CL=2.5 DQS DQ DM DOa-n tDQSS (min) Dla-b DO a-n = data out from bank a, column n . a-b = data in to bank a, column b DI 1 subsequent elements of data out appear in the programmed order following DO a-n. Data In elements are applied following Dl a-b in the programmed order, according to burst length. Shown with nominal t AC, tDQSCK , and tDQSQ. Don't Care REV 1.3 .com 06/2003 30 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Read to Precharge: CAS Latencies (Burst Length = 4 or 8) CAS Latency = 3 CK CK Command Read NOP PRE NOP NOP ACT tR P Address BA a, COL n BA a or all BA a, ROW CL=3 DQS DQ DOa-n CAS Latency = 2.5 CK CK t4U.com Command Read NOP PRE .com NOP NOP ACT DataShee tR P Address BA a, COL n BA a or all BA a, ROW CL=2.5 DQS DQ DOa-n DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal t AC , tDQSCK , and tDQSQ . Don't Care REV 1.3 .com 06/2003 31 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 4 D a t a S h e e tU . c o m www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Writes Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 33. The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled. During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS ) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. t DQSS (min) and tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 34 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored. Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Timing figure Write to Write (Burst Length = 4) on page 35 shows concatenated bursts of 4. An example of nonconsecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 36. Fullspeed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst Length = 2, 4 or 8) on page 37. Data for any Write burst may be followed by a subsequent Read command. To follow a Write without truncating the write burst, t WTR (Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting (CAS Latency = 3; Burst Length = 4) on page 38. .com t4U.com "Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)", "Write to Read: Minimum D QSS , Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)", and "Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)". Note that only the data-in pairs that are registered prior to the t WTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously. Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write burst, t WR should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 42. Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 43 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8) on page 45. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts. Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures DataShee REV 1.3 .com 06/2003 32 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write Command CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 HIGH CA EN AP A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care t4U.com .com DataShee REV 1.3 .com 06/2003 33 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 4 DataSheet U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write Burst (Burst Length = 4) Maximum DQSS T1 CK CK Command Address Write BA a, COL b T2 T3 T4 NOP NOP NOP tDQSS (max) DQS DQ DM tQCSW (max) QFC (Optional) tQCHW (min) Dla-b Minimum DQSS t4U.com T1 CK CK Command Address Write BA a, COL b T2 .com T3 T4 DataShee NOP NOP NOP tDQSS (min) DQS DQ DM tQCSW (max) QFC tQCHW(max) Dla-b DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a- b. A non-interrupted burst is shown. A10 is Low with the Write command (Auto Precharge is disabled). QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to V DDQ . Don't Care REV 1.3 .com 06/2003 34 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Write (Burst Length = 4) Maximum DQSS T1 CK CK Command Address Write NOP Write NOP NOP NOP T2 T3 T4 T5 T6 BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DI a-b DI a-n Minimum DQSS T1 CK CK Command Address Write NOP Write NOP NOP NOP t4U.com T2 .com T3 T4 T5 T6 DataShee BA, COL b BA, COL n tDQSS (min) DQS DQ DM DI a-b DI a-n DI a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank. Don't Care REV 1.3 .com 06/2003 35 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) T1 CK CK Command Address Write T2 T3 T4 T5 NOP NOP Write NOP BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DI a-b DI a-n DI a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank. Don't Care t4U.com .com DataShee REV 1.3 .com 06/2003 36 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Random Write Cycles (Burst Length = 2, 4 or 8) Maximum DQSS T1 CK CK Command Address Write Write BAa, COL x T2 T3 T4 T5 Write BAa, COL n Write BAa, COL a Write BAa, COL g BAa, COL b tDQSS (max) DQS DQ DM DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a' Minimum D QSS t4U.com CK CK Command Address T1 T2 T3 .com T4 T5 DataShee Write Write BAa, COL x Write BAa, COL n Write BAa, COL a Write BAa, COL g BAa, COL b tDQSS (min) DQS DQ DM DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a' DI a-g DI a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted). Each Write command may be to any bank. Don't Care REV 1.3 .com 06/2003 37 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Read: Non-Interrupting (CAS Latency = 3; Burst Length = 4) Maximum D QSS T1 CK CK Command Write NOP NOP NOP Read NOP T2 T3 T4 T5 T6 tWTR Address BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DI a- b CL = 3 Minimum D QSS t4U.com CK CK Command T1 T2 .com T3 T4 T5 T6 DataShee Write NOP NOP NOP Read NOP tWTR Address BAa, COL b BAa, COL n tDQSS (min) DQS DQ DM DI a- b CL = 3 DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWTR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands may be to any bank. Don't Care REV 1.3 .com 06/2003 38 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 4 DataSheet U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Read: Interrupting (CAS Latency = 3; Burst Length = 8) Maximum DQSS T1 CK CK Command Write NOP NOP NOP Read NOP T2 T3 T4 T5 T6 tW T R Address BAa, COL b BAa, COL n tDQSS (max) DQS DQ DM DIa- b CL = 3 1 1 t4U.com T1 CK CK Command Write NOP .com T2 T3 T4 Minimum D QSS T5 T6 DataShee NOP NOP Read NOP tWTR Address BAa, COL b BAa, COL n tDQSS (min) DQS DQ DM DI a-b CL = 3 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low. Don't Care REV 1.3 .com 06/2003 39 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 3; Burst Length = 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP Read NOP tW T R Address BAa, COL b BAa, COL n tDQSS (min) DQS DQ DM DI a-b CL = 3 1 2 2 t4U.com DI a- b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following DI a-b . .com tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element) The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = This bit is correctly written into the memory array if DM is low. Don't Care 2 = These bits are incorrectly written into the memory array if DM is low. DataShee REV 1.3 .com 06/2003 40 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Read: Nominal DQSS, Interrupting (CAS Latency = 3; Burst Length = 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP Read NOP tWTR Address BAa, COL b BAa, COL n tDQSS (nom) DQS DQ DM DI a- b CL = 3 1 1 t4U.com DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair. .com The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low. DataShee Don't Care REV 1.3 .com 06/2003 41 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Precharge: Non-Interrupting (Burst Length = 4) Maximum D QSS T1 CK CK Command Write NOP NOP NOP NOP PRE T2 T3 T4 T5 T6 tWR Address BA a, COL b BA (a or all) tDQSS (max) DQS DQ DM DI a-b tRP Minimum DQSS t4U.com CK CK Command T1 T2 .com T3 T4 T5 T6 DataShee Write NOP NOP NOP NOP PRE tWR Address BA a, COL b BA (a or all) tDQSS (min) DQS DQ DM DI a-b tRP DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). Don't Care REV 1.3 .com 06/2003 42 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Precharge: Interrupting (Burst Length = 4 or 8) Maximum D QSS T1 CK CK Command Write NOP NOP NOP PRE NOP T2 T3 T4 T5 T6 tWR Address BA a, COL b BA (a or all) tDQSS (max) DQS DQ DM DI a-b 2 tR P 3 3 1 1 Minimum DQSS t4U.com CK CK Command T1 T2 .com T3 T4 T5 T6 DataShee Write NOP NOP NOP PRE NOP tWR Address BA a, COL b BA (a or all) tDQSS (min) DQS DQ DM DI a-b 2 tR P 3 3 1 1 DI a- b = data in for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst, for burst length = 8. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low. Don't Care REV 1.3 .com 06/2003 43 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting (Burst Length = 4 or 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP PRE NOP tWR Address BA a, COL b BA (a or all) tDQSS (min) DQS DQ DM DI a-b 2 tRP 3 4 4 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written. tWR is referenced from the first positive CK edge after the last desired data in pair. t4U.com .com The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = This bit is correctly written into the memory array if DM is low. 4 = These bits are incorrectly written into the memory array if DM is low. DataShee Don't Care REV 1.3 .com 06/2003 44 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8) T1 CK CK Command Write T2 T3 T4 T5 T6 NOP NOP NOP PRE NOP tWR Address BA a, COL b BA (a or all) tDQSS (nom) DQS DQ DM DI a-b 2 tRP 3 3 1 1 DI a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. t4U.com The Precharge command masks the last 2 data elements in the burst. .com A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low. DataShee Don't Care REV 1.3 .com 06/2003 45 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Precharge Command CK CK CKE CS RAS CAS WE A0-A9, A11, A12 All Banks A10 BA0, BA1 One Bank BA BA = bank address (if A10 is Low, otherwise Don't Care). Don't Care HIGH t4U.com Precharge .com DataShee The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. REV 1.3 .com 06/2003 46 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Power Down Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in any bank, this mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power Down. In that case, the DLL must be enabled after exiting Power Down, and 200 clock cycles must occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are "Don't Care". However, Power Down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled Power Down mode. The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid, executable command may be applied one clock cycle later. Power Down CK CK tIS tIS CKE Command VALID No column access in progress NOP NOP Exit power down mode tPDEX VALID t4U.com .com DataShee Enter Power Down mode (Burst Read or Write operation must not be in progress) Don't Care REV 1.3 .com 06/2003 47 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Truth Table 2: Clock Enable (CKE) 1. 2. 3. 4. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. Command n is the command registered at clock edge n, and action n is a result of command n. All states and sequences not shown are illegal or reserved. CKE n-1 Current State Previous Cycle L L L L H H H H CKEn Current Cycle L H L H L L L H Command n Action n Notes Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active X Deselect or NOP X Deselect or NOP Deselect or NOP Auto Refresh Deselect or NOP See "Truth Table 3: Current State Bank n - Command to Bank n (Same Bank) " on page 49 Maintain Self-Refresh Exit Self-Refresh Maintain Power Down Exit Power Down Precharge Power Down Entry Self Refresh Entry Active Power Down Entry 1 1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t XSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock. t4U.com .com DataShee REV 1.3 .com 06/2003 48 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Truth Table 3: Current State Bank n - Command to Bank n (Same Bank) Current State Any L L Idle L L L Row Active L L Read (Auto Precharge Disabled) L L L Write (Auto Precharge Disabled) L L L H L L L H H L H L H H H L H H L L L L H L H H L L H H H H L H L L H L L H L L No Operation Active Auto Refresh Mode Register Set Read Write Precharge Read Precharge Burst Terminate Read Write Precharge Select column and start Read burst Select column and start Write burst Deactivate row in bank(s) Select column and start new Read burst Truncate Read burst, start Precharge Burst Terminate Select column and start Read burst Select column and start Write burst Truncate Write burst, start Precharge NOP. Continue previous operation Select and activate row 1-6 1-6 1-7 1-7 1-6, 10 1-6, 10 1-6, 8 1-6, 10 1-6, 8 1-6, 9 1-6, 10, 11 1-6, 10 1-6, 8, 11 CS H RAS X CAS X WE X Command Deselect Action NOP. Continue previous operation Notes 1-6 t4U.com 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed .com to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and t RP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when t R P is met. Once t RP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when t RCD is met. Once t RCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t RP has been met. Once t RP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once t RP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4. 5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when t RFC is met. Once t RFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once t MRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when t RP is met. Once t RP is met, all banks is in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank. 10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 11. Requires appropriate DM masking. DataShee REV 1.3 .com 06/2003 49 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Truth Table 4: Current State Bank n - Command to Bank m (Different bank) (Part 1 of 2) Current State Any L Idle X L Row Activating, Active, or Precharging L L L Read (Auto Precharge Disabled) L L L L Write (Auto Precharge Disabled) L L L H X L H H L L H L L H H L H X H L L H H L H H L L H H X H H L L H H L H H L L No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge Select and activate row Select column and start Read burst Select column and start new Write burst Select and activate row Select column and start new Read burst Select and activate row Select column and start Read burst Select column and start Write burst NOP/continue previous operation 1-6 1-6 1-6 1-7 1-7 1-6 1-6 1-7 1-6 1-6 1-8 1-7 1-6 CS H RAS X CAS X WE X Command Deselect Action NOP/continue previous operation Notes 1-6 t4U.com 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been .com met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and t RP has been met. Row Active: A row in the bank has been activated, and t RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or t R P) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided). DataShee REV 1.3 .com 06/2003 50 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Truth Table 4: Current State Bank n - Command to Bank m (Different bank) (Part 2 of 2) Current State CS L Read (With Auto Precharge) L L L L Write (With Auto Precharge) L L L RAS L H H L L H H L CAS H L L H H L L H WE H H L L H H L L Command Active Read Write Precharge Active Read Write Precharge Select and activate row Select column and start Read burst Select column and start new Write burst Action Select and activate row Select column and start new Read burst Select column and start Write burst Notes 1-6 1-7,10 1-7,9,10 1-6 1-6 1-7,10 1-7,10 1-6 t4U.com 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and t RP has been met. Row Active: A row in the bank has been activated, and t RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. .com Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or t R P) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided). DataShee REV 1.3 .com 06/2003 51 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Simplified State Diagram Power Applied Power On Precharge Preall Self Refresh REFS REFSX MRS EMRS MRS Idle REFA Auto Refresh CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL t4U.com Write .com Row Active Read Burst Stop DataShee Write A Write Read A Read Read Write A Read A Write A PRE PRE PRE Read A Read A PRE Precharge Preall Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge REV 1.3 .com 06/2003 52 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Absolute Maximum Ratings Symbol V IN , V OUT VI N V DD V DDQ TA T STG PD IOUT Parameter Voltage on I/O pins relative to VSS Voltage on Inputs relative to VSS Voltage on V D D supply relative to VSS Voltage on V DDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating Units V V V V -0.5 to V DDQ + 0.5 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 0 to +70 C C W mA -55 to +150 1.0 50 Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DQS/DQ/DM Slew Rate Parameter Symbol DDR400 (-5) Min DCS/DQ/DM input slew rate DC SLEW TBD Max TBD V/ns 1, 2 Unit Notes t4U.com .com DataShee 1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC). 2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transition through the DC region must be monotonic. REV 1.3 .com 06/2003 53 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Capacitance Parameter Input Capacitance: CK, CK Delta Input Capacitance: CK, CK Input Capacitance: All other input-only pins (except DM) Delta Input Capacitance: All other input-only pins (except DM) Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS, DM Symbol CI 1 delta CI 1 CI 2 delta CI 2 C IO delta C IO 4.0 2.0 Min. 2.0 Max. 3.0 0.25 3.0 0.5 5.0 0.5 Units pF pF pF pF pF pF Notes 1 1 1 1 1, 2 1 1. V DDQ = V D D = 2.6V 0.1V (minimum range to maximum range), f = 100MHz, TA = 25C, VO DC = V DDQ/2 , VOPeak -Peak =0.2V. 2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match input propagation times of DQ, DQS and DM in the system. DC Electrical Characteristics and Operating Conditions (0C TA 70x C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V, see AC Characteristics) Symbol V DD V DDQ V SS , VSSQ Supply Voltage I/O Supply Voltage Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs V-I Matching Pullup Current to Pulldown Current Ratio Input Leakage Current Any input 0V V IN V D D; (All other pins not under test Output Leakage Current (DQs are disabled; 0V V out V DDQ Output Current: Nominal Strength Driver High current (VOUT = V DDQ -0.373V, min V REF, min VTT ) Low current (VOUT = 0.373V, max V REF, max V TT ) Parameter Min 2.5 2.5 0 Max 2.7 2.7 0 0.51 x V DDQ V REF + 0.04 V DDQ + 0.3 V REF - 0.15 V DDQ + 0.3 V DDQ + 0.6 V DDQ + 0.6 1.4 5 5 A A Units V V V V V V V V V V 1, 2 1, 3 1 1 1 1, 4 1, 4 5 1 1 Notes 1 1 t4U.com V REF V TT V IH(DC) V IL(DC) V IN(DC) V ID(DC) V IX(DC) VI Ratio II IOZ IO H IOL .com 0.49 x V DDQ V REF - 0.04 V REF + 0.15 - 0.3 - 0.3 0.30 0.30 0.71 DataShee = 0V) -5 -5 - 16.8 mA 16.8 1 1. Inputs are not recognized as valid until V REF stabilizes. 2. V REF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. V TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of V REF . 4. V ID is the magnitude of the difference between the input level on CK and the input level on CK . 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. REV 1.3 .com 06/2003 54 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM DC Electrical Characteristics and Operating Conditions (0C TA 70x C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V, see AC Characteristics) Symbol IOHW IOLW Parameter Output Current: Half- Strength Driver High current (VOUT = V DDQ -0.763V, min V REF, min VTT ) Low current (VOUT = 0.763V, max V REF, max V TT ) Min - 9.0 mA 9.0 1 Max Units Notes 1. Inputs are not recognized as valid until V REF stabilizes. 2. V REF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. V TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of V REF . 4. V ID is the magnitude of the difference between the input level on CK and the input level on CK . 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. Normal Strength Driver Pulldown and Pullup Characteristics 1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 2. It is recommended that the "typical" IBIS pulldown V-I curve lie within the shaded region of the V-I curve. Normal Strength Driver Pulldown Characteristics 140 Maximum t4U.com IOUT (mA) .com DataShee Typical High Typical Low Minimum 0 0 VOUT (V) 2.7 3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 4. It is recommended that the "typical" IBIS pullup V-I curve lie within the shaded region of the V-I curve. REV 1.3 .com 06/2003 55 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Normal Strength Driver Pullup Characteristics 0 Minimum IOUT (mA) Typical Low Typical High -200 0 VOUT (V) 2.7 Maximum 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity + 10%, for device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed. 7. These characteristics are intended to obey the SSTL_2 class II standard. 8. This specification is intended for DDR SDRAM only. t4U.com .com DataShee REV 1.3 .com 06/2003 56 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Normal Strength Driver Pulldown and Pullup Currents Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 Typical Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Typical High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Min 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Max 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 Typical Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Typical High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Min -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Max -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2 t4U.com 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 .com 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 103.8 DataShee Normal Strength Driver Evaluation Conditions Typical Temperature (T ambient) V DDQ Process conditions 25 C 2.5V typical process Minimum 70 C 2.3V slow-slow process Maximum 0 C 2.7V fast-fast process REV 1.3 .com 06/2003 57 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I DD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to V S S. 2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and I DD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level. AC Output Load Circuit Diagrams V TT 50 Output (V OUT ) Timing Reference Point t4U.com .com 30pF DataShee REV 1.3 .com 06/2003 58 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM AC Input Operating Conditions (0 C T A 70 C; VDDQ = +2.6V 0.1V; VDD = +2.6V 0.1V, See AC Characteristics) Symbol V IH(AC) V IL(AC) V ID(AC) V IX(AC) Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS, and DM Signals Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs 0.62 0.5*V DDQ - 0.2 Min V REF + 0.31 V REF - 0.31 V DDQ + 0.6 0.5*V DDQ + 0.2 Max Unit V V V V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4 1. Input slew rate = 1V/ns . 2. Inputs are not recognized as valid until VREF stabilizes. 3. V ID is the magnitude of the difference between the input level on CK and the input level on CK . 4. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. IDD Specifications and Conditions (0 C T A 70 C; VDDQ = +2.6V 0.1V; VDD = +2.6V 0.1V, See AC Characteristics) DDR400A (-5) tCK =5ns 115 DDR400B (-5T) tCK =5ns 115 Symbol Parameter/Condition Unit Notes IDD0 Operating Current: one bank; active / precharge; tRC = t R C (min); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active / read / precharge; Burst = 2; t RC = tR C (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once .com per clock cycle Precharge Power Down Standby Current: all banks idle; Power Down mode; CKE V IL (max) Idle Standby Current: CS V I H (min); all banks idle; CKE V IH (min); address and control inputs changing once per clock cycle Active Power Down Standby Current: one bank active; Power Down mode; CKE V IL (max) Active Standby Current: one bank; active / precharge; CS V IH (min); CKE V I H (min); tRC = t RAS (max); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5 Auto-Refresh Current: tRC = tRFC (min) Self-Refresh Current: CKE 0.2V Operating current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA. mA 1 t4U.com IDD1 120 120 mA 1 DataShee IDD2P IDD2N 20 45 20 45 mA mA 1 1 IDD3P 21 21 mA 1 IDD3N 75 75 mA 1 IDD4R 200 200 mA 1 IDD4W IDD5 IDD6 195 225 3 195 225 3 mA mA mA 1 1 1, 2 IDD7 325 325 mA 1 1. IDD specifications are tested after the device is properly initialized. 2. Enables on-chip refresh and address counters. REV 1.3 .com 06/2003 59 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Electrical Characteristics & AC Timing - Absolute Specifications DDR400 (-5) Min tAC tDQSCK tCH tCL tCK DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CL = 3.0 Clock cycle time CL = 2.5 DQ and DM input hold time DQ and DM input setup time Input pulse width DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK DQS-DQ skew (DQS & associated DQ signals) TSOP Package 5 0.4 0.4 2.2 1.75 - 0.6 - 0.6 + 0.6 + 0.6 + 0.4 + 0.4 12 - 0.6 - 0.5 0.45 0.45 5 Max + 0.6 + 0.5 0.55 0.55 8 (0 C T A 70 C; VDDQ = +2.6V 0.1V; VDD = 2.6V 0.1V, See AC Characteristics) (Part 1 of 2) DDR400 (-5T) Min - 0.65 - 0.55 0.45 0.45 5 6 0.4 0.4 2.2 1.75 - 0.6 - 0.6 + 0.6 + 0.6 + 0.4 + 0.4 min (tCL , tCH) tHP - tQHS 0.5 0.5 0.72 0.35 0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.6 0.7 0.60 1.28 0.72 0.35 0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.6 0.7 0.60 0.5 0.5 1.28 Max + 0.65 + 0.55 0.55 0.55 8 ns 12 ns ns ns ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns tCK tCK ns ns ns 1-4, 15, 16 1-4, 15, 16 2-4, 12 1-4 1-4, 5 1-4, 5 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, 10, 11, 12, 14 1-4 ns ns tCK tCK 1-4 1-4 1-4 1-4 Symbol Parameter Unit Notes tDH tDS tIPW tDIPW tH Z tLZ t4U.com tDQSQ .com min (t CL , tCH) tHP - tQHS BGA Package DataShee tHP tQH tQ H S Minimum half clk period for any given cycle; defined by clk high (t CH) or clk low (t C L) time Data output hold time from DQS Data hold Skew Factor Write command to 1st DQS latching transition DQS input high pulse width (write cycle) DQS input low pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) TSOP Package BGA Package tDQSS tDQSH tDQSL tDSS tDSH tM R D tWPRES tWPST tWPRE tIH tIS tIH REV 1.3 .com 06/2003 60 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Electrical Characteristics & AC Timing - Absolute Specifications DDR400 (-5) Min tIS tRPRE tRPST tRAS tRC tR F C tRCD tRAP tRP tRRD tWR tDAL Address and control input setup time (slow slew rate) Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Autoprecharge Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Power down exit time Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval 0.7 0.9 0.40 40 55 70 15 min (t RCD, tRAS ) 15 10 15 (t WR /tCK ) + (t RP/tCK ) 1.1 0.60 120,000 Max Min 0.7 0.9 0.40 40 55 70 15 min (t RCD, tRAS ) 15 10 15 (t WR /tCK ) + (t RP /tCK ) 2 5 75 200 7.8 7.8 1.1 0.60 120,000 (0 C T A 70 C; VDDQ = +2.6V 0.1V; VDD = 2.6V 0.1V, See AC Characteristics) (Part 2 of 2) DDR400 (-5T) Max ns tCK tCK ns ns ns ns ns ns ns ns tCK tCK ns ns tCK s 2-4, 10, 11, 12, 14 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 13 1-4 1-4 1-4 1-4 1-4, 8 Symbol Parameter Unit Notes t4U.com tW T R tPDEX tXSNR tXSRD tREFI 2 .com 5 75 200 DataShee REV 1.3 .com 06/2003 61 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Electrical Characteristics & AC Timing - Absolute Specifications Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. t4U.com 13. Input slew rate = 1V/ns. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VREF . Inputs are not recognized as valid until VREF stabilizes. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT . tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. For command/address input slew rate 1.0V/ns. Slew rate is measured between V OH (AC) and VOL (AC). For command/address input slew rate 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). CK/CK slew rates are 1.0V/ns. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. .com For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal DataShee to the actual system clock cycle time. For example, for DDR266B at CL = 2.5, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = 2+ 3 = 5. REV 1.3 .com 06/2003 62 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta (t IS ) 0 +50 +100 delta (tIH ) 0 0 0 IL (AC) Unit ps ps ps or V IH (DC) to V IL (DC), Notes 1,2 1,2 1,2 similarly for rising 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta (t D S) 0 +75 +150 delta (t DH ) 0 +75 +150 IL (AC) or Unit ps ps ps V IH (DC) to Notes 1,2 1,2 1,2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V transitions. V IL (DC), similarly for rising 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. t4U.com .com 16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. Input Slew Rate 0.0 V/ns 0.25 V/ns 0.5 V/ns delta (t D S) 0 +50 +100 delta (t DH ) 0 +50 +100 IL (AC) DataShee Unit ps ps ps or V IH (DC) to V IL (DC), Notes 1,2,3,4 1,2,3,4 1,2,3,4 similarly for rising 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 1.3 .com 06/2003 63 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Package Dimensions (400mil; 66 lead; Thin Small Outline Package) Detail A 22.22 0.10 10.16 . 0.13 Lead #1 t4U.com .com Seating Plane 11 .76 0.20 DataShee 0.10 0.65 Basic 0.30 + 0.03 - 0.08 0.71REF Detail A 1.20 Max 0.25 Basic Gage Plane 0.5 0.1 0.05 Min REV 1.3 .com 06/2003 64 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Package Dimensions (60 balls; 0.8mmx1.0mm Pitch; CSP Package) 8.0 0.80 0.80 0.50 Dia. 0.45 1.00 t4U.com 1.60 .com 0.35 1.15 1.0 13.0 DataShee Note : All dimensions are typical unless otherwise stated. Unit : Millimeters REV 1.3 .com 06/2003 65 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Revision Log Rev 0.1 0.2 Date 01/2003 02/2003 Preliminary Release Updated tQHS from 0.55ns to 0.5ns in Electrical Characteristics & AC Timing Table Updated IDD values in IDD Specifications and Conditions Table Removed CL2 support Modification 1.0 03/2003 Added DDR400B (-5T) speed grade Official Release 1.1 1.2 1.3 1.4 04/2003 05/2003 06/2003 10/2003 Fixed typo for tWTR in Electrical Characteristics & AC Timing Table Added Lead-free and Halogen-free component part numbers Fixed various typos regarding CAS Latency 3 support Removed CAS Latency 2.5 support t4U.com .com DataShee REV 1.3 .com 06/2003 66 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www..com (R) Nanya Technology Corporation. All rights reserved. Printed in Taiwan, R.O.C. June 2002 The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both. NANYA NANYA logo Other company, product and service names may be trademarks or service marks of others. NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC's standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. t4U.com Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards. NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. .com NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C. The NANYA TECHNOLOGY CORPORATION home page can be found at http:\\www.nanya.com .com DataSheet4 U .com |
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